A conventional clock and data recovery circuit of this type will now be described. FIG. 8 is a diagram showing the configuration of a clock and data recovery circuit of the type disclosed in Patent Publication 1 as indicated below. Referring to FIG. 8, this clock and data recovery circuit includes a phase detector 602 for comparing the phase of two input signals to output the result of comparison, an integrator circuit 603 for integrating a signal representing the result of phase comparison, and a voltage-controlled oscillator 604, abbreviated to VCO, for varying the oscillation frequency based on an output voltage from the integrator circuit 603. These circuit components make up a feedback loop (feedback closed path) 601. The integrator circuit 603 is composed by a low-pass filter and may also be termed a ‘loop filter circuit’, which may also be abbreviated to ‘LPF’.
An output signal of the VCO 604 is fed back to one input end of the phase detector 602. To the other input of the phase detector 602 is supplied an input data signal (Data In).
In the clock and data recovery circuit, there is provided a discriminator 605 for discriminating and recovering the input data signal. The discriminator 605 is composed by, for example, a D-type flip-flop (edge-triggered register) which samples the input data signal (Data In), supplied to a data input terminal, with a rising or fall edge of a discriminating clock signal, supplied to a clock input end, to output the sampled result as an output data signal (Data Out) at a data output terminal. The discriminator 605 is also termed a ‘D-FF’, a ‘re-timer’ or a ‘decision circuit’. The discriminator 605 receives, at its clock input terminal, an output clock signal (Clock Out; clock for discrimination) from the VCO 604, and is synchronized with the output clock signal from the VCO 604. The integrator circuit 603 has a sufficiently long time constant as compared with the clock period of the transmission data signal.
The operation of a conventional clock and data recovery circuit, shown in FIG. 8, will now be described.
FIG. 9 is a diagram showing phase comparison characteristics of the phase detector 602 of FIG. 8. In FIG. 9, the phase difference and an output of the phase detector are plotted on the horizontal axis and on the vertical axis, respectively. The clock period of the transmission data signal is assumed to be 2π. If the phase difference φ between the input data signal (Data In) and the clock for discrimination (CLOCK OUT), as an output of the VCO 604, is such that −π<φ<0, the phase detector 602 outputs a negative output. If the phase difference φ is such that 0 <φ<π, the phase detector 602 outputs a positive output.
If, on the other hand, there is no phase difference between two signals, supplied to two input terminals of the phase detector 602 (φ=0), the output of the phase detector 602 becomes equal to zero.
The VCO 604 receives the feedback from the output of the phase detector 602 and varies the oscillation frequency in a direction of reducing the phase difference φ within a range of −π/2 <φ<π/2, until finally the phase difference φ is equal to zero in which synchronization is attained.
FIGS. 10A to 10C show the above-described process by timing charts. FIG. 10A shows the timing chart for a case where there is phase lead in the clock for discrimination (=output clock of the VCO 604). The phase detector 602 compares the phase of a change-point of an input data signal in this case with a fall timing of the clock for discrimination, and outputs a negative value corresponding to the phase difference. The integrator circuit 603 integrates an output of the phase detector 602 with a time constant which is long enough as compared with the period of the data signal for transmission. Hence, the output gradually transitions to a low level. An output of the integrator circuit 603 is supplied as a control voltage signal to the VCO 604 to lower the oscillation frequency. By this feedback configuration, the phase difference φ is decreased in a direction in which the change-point of input data is ultimately coincident with the fall timing of the clock for discrimination.
FIG. 10B shows the timing chart for a case where there is phase lag in the clock for discrimination (=output clock of VCO 604). The phase detector 602 outputs a positive value, as before, so that the output of the integrator circuit 603 gradually transitions to a high level. This raises the oscillation frequency of the VCO 604, with the phase difference φ decreasing in a direction in which the change-point of the input data is ultimately coincident with the fall timing of the clock for discrimination.
FIG. 10C shows the timing chart for a synchronized state where the change-point of the input data signal has become coincident with the fall timing of the clock for discrimination. In this case, the phase detector 602 and the integrator circuit 603 both output zero, and the oscillation frequency of the VCO 604 then is fixed. Thus, the change-point of the input data is kept at all times coincident with the fall timing of the clock for discrimination.
The conventional clock data recovering device, described above, converges to a synchronized state in which the change-point of the input data is coincident with the fall timing of the clock for discrimination. Hence, the clock signal (Clock Out), synchronized with the input data signal (Data In), may be recovered.
Also, in the discriminator 605, the data signal may be discriminated and recovered with an optimum phase of discrimination through use of the recovered clock signal (Clock Out).
FIG. 11 is a diagram showing the configuration of a clock and data recovery circuit disclosed in Patent Publication 1, recited hereinbelow. Referring to FIG. 11, the conventional clock and data recovery circuit will now be described. A clock extraction means 901 extracts a change-point signal from a transmission data signal. A phase synchronization means 902 synchronizes the oscillation frequency of a voltage controlled oscillator (VCO) 909 with the transmission data signal, based on the change-point signal. A clock delay means 903 performs phase-comparison between the transmission data signal and the output clock of a variable delay circuit 912, by a phase detector 910, to delay the clock by a certain time period.
In the discriminator 904, the transmission data signal is discriminated and recovered with the clock supplied from the clock delay means 903. By this configuration, the clock may automatically be delayed by a certain time period with respect to the change-point of transmission data signal.
There is also known a phase synchronizing circuit composed of a phase synchronizing loop circuit, a phase shifter, a retiming circuit and a phase shift control circuit (see Patent Publication 2, for example). The phase synchronizing loop circuit outputs a VCO oscillation signal, as a clock signal phase-synchronized with the data input signal (DATA IN), and the phase shifter outputs a clock signal for the data input signal. The retiming circuit has a discriminating/recovering function of outputting an as-retimed discriminated /recovered signal, as retimed data, and outputs a data signal (DATA OUT). The phase shift control circuit receives the extracted clock, generated by the phase synchronizing loop circuit, at its data latch circuit, via the phase shifter, and latches a signal level, using a data input signal, to generate the phase information. The present invention, which will be described subsequently, differs from the configuration of Patent Publication 2 as to e.g. the phase shift control and structure. For example, in one aspect of the present invention, which will be described in detail, the phase difference between the output data signal (DATA OUT) from the discriminator (which samples received data with the output clock signal) and the input data signal (DATA IN) is checked by a phase detector, and the phase of the oscillation signal from the VCO is shifted based on the result of phase comparison. On the other hand, in the configuration described in Patent Publication 2, the phase shift control circuit controls the phase of the phase shifter based on an output value of a latch which latches the input data signal (DATA IN) with an output clock signal.
Non-Patent Publication 1: ‘Design of Integrated Circuits for Optical Communications’, ISBN0-07-282258-9, pp.297
Patent Publication 1: JP Patent Kokai Publication No. JP-P2000-228660A (page 6, FIG. 6)
Patent Publication 2: JP Patent Kokai Publication No. JP-P2000-216763A (pages 5 and 6, FIG. 1)